1. Technical Field
The present disclosure relates to a driver circuit and method for reducing electromagnetic interference (EMI) without affecting communication delays in a driver stage.
More particularly, the present disclosure relates to a driver circuit and method for switching a load through a power transistor.
2. Description of the Related Art
External inductive loads 1 connected to a high voltage power line Vin are known to be driven, see FIGS. 1a and 1b, using a switch 2 and an appropriate driver stage 3.
The switch 2 may be commonly implemented, if allowed by the manufacturing conditions and technology, as an integrated MOSFET transistor, such as a power MOSFET or an IGBT.
Particularly, referring to FIG. 1a, in case of low-side drive, the transistor 2 has:                the gate terminal driven by two current generators I1 and I2 that are part of the driver stage 3, which are in turn controlled by respective control signals S1 and S2,        the grounded source terminal, and        the drain terminal connected to the external inductive load 1.        
Otherwise, referring to FIG. 1b, in case of high-side drive, the transistor 2 has:                the gate terminal driven by two current generators I1 and I2 that are part of the driver stage 3, which are in turn controlled by respective control signals S1 and S2,        the source terminal connected to the reference terminal of the driver stage and to the external inductive load 1, and        the drain terminal connected to high-voltage power supply Vin.        
Still referring to such FIGS. 1a and 1b, there are also shown the capacitances of the transistor between the gate terminal and the source terminal CGS and between the gate terminal and the drain terminal CGD, whose effects on operation will be more apparent from the following description.
For simplicity, reference will be made herein to the low-side drive case, considering that this description may also relate to high-side driving.
As is known to those of ordinary skill in the art, MOSFET devices have been increasingly used in electronic circuits due to their being easily driven and to their ability of handing high currents and voltages at high switching frequencies.
Nonetheless, power dissipation in the power transistor 3 may be reduced by increasing the switching speed, but this involves increased generation of electromagnetic interference (EMI).
When voltage and current slopes are increased during switching transients, the EMI level also increases, wherefore the design of any power driving stage requires a reasonable compromise of the characteristics of the device, power losses and EMI.
The switching speed of a MOSFET device is strictly related to the amount of the charge that is transmitted to the dynamic capacitance within the gate terminal CG, whose value is equal to the sum of those of the dynamic capacitances situated between the gate and source and drain terminals, i.e. CG=CGS+CGD.
Furthermore, it should be noted that by imparting an appropriate form to the gate current iG, voltage slopes may be controlled at the drain terminal, in case of low-side drive and at the source terminal, in case of high-side drive.
Considering the low-side case (see FIG. 1a), the drain voltage VD may be gradually increased and decreased by adjusting, during design, the current value that is used for charging and discharging the dynamic input capacitance CG of the power MOSFET.
Although the capacitance CGS is an important parameter, the capacitance CGD is much more significant, because it is a nonlinear capacitance, that changes as a function of the voltage at the drain terminal.
The effect of the capacitance CGD is similar to the Miller effect (which is well known to the skilled person and will not be further described herein) and affects the total input impedance of the power MOSFET 2, wherefore the total dynamic input capacitance is generally higher than the sum of static capacitances.
Therefore, the capacitance CGD, which is lower than the capacitance CGS in its static value, may assume a dynamic value about 20 times as high as the capacitance CGS.
This means that the capacitance CGD or “Miller” capacitance typically has a higher charge than the static input capacitance.
Therefore, the upslope and downslope time of the drain voltage may be controlled using the Miller effect.
The slope of the drain voltage VD depends on the current generated or absorbed at the gate of the power transistor 2, i.e. on the value of the gate current iG, which may be expressed by the following relation:
                              i          G                =                                            i              CGS                        +                          i              CGD                                =                                                    ⅆ                                  (                                                            C                      GS                                        ·                                          v                      GS                                                        )                                                            ⅆ                t                                      +                                          ⅆ                                  (                                                            C                      GD                                        ·                                          v                      GD                                                        )                                                            ⅆ                t                                                                        (        1        )            where iCGS and iCGD represent the currents flowing into the capacitances CGS and CGD respectively.
As a consequence of the Miller effect, the voltage VGS between the gate and source terminals may be deemed to be constant and the equation (1) may be rewritten as:
                                                                        i                G                            =                            ⁢                                                C                                      GD                    Miller                                                  ·                                                      ⅆ                                          v                      GD                                                                            ⅆ                    t                                                                                                                          =                            ⁢                                                C                                      GD                    Miller                                                  ·                                                      ⅆ                                          (                                                                        v                          GS                                                -                                                  v                          DS                                                                    )                                                                            ⅆ                    t                                                                                                                          =                            ⁢                                                -                                      C                                          GD                      Miller                                                                      ·                                                      ⅆ                                          v                      DS                                                                            ⅆ                    t                                                                                                          (        2        )            
Furthermore, the voltage between the gate and the source may be determined in this state.
Particularly, since the gate current iG is also constant, according to the input transfer feature, i.e. according to the following relation:iD=gm·(vGS−vTH),where iD is the drain current, gm is the transconductance of the transistor and vTH is the threshold voltage, the voltage VGS, Miller may be rewritten as follows:
                              v                      GS            Miller                          =                                            i              D                                      g              m                                +                      v            TH                                              (        3        )            
A variety of circuit implementations are known in the art, which are designed to utilize the Miller effect for switching speed control.
Particularly, in one implementation, the gate terminal of the power transistor is driven via a constant current source, by limiting the voltage VGS charging and discharging speed, thereby reducing the drain voltage slope.
Nonetheless, this gate terminal driving technique involves a high power-off delay Td, wherefore this technique cannot be used in power applications, whose specifications require fast switching times.
Thus, also referring to FIG. 2, which shows the switching waveforms with the inductive load 1 connected to the drain terminal of the MOSFET transistor, if the control signal V(QG) of the driver stage becomes so low that the MOSFET is powered off, a constant current is absorbed and the voltage V(GATE) at the gate terminal discharges slowly.
During this period of time Td, the drain current I (DRAIN) keeps on increasing, thereby causing consumptions and delays in MOSFET transistor switching, until the V(GATE) reaches the Miller zone.
Now, the voltage at the drain terminal V(DRAIN) increases to the maximum value allowed by the power supply voltage Vin.